The present invention relates to semiconductor devices, and more particularly to a method and system for making a more easily discernable alignment mark for thin layers, such as the tunnel oxide layer, in memory devices such as flash memory devices.
Current generation semiconductor devices, such as flash memory devices, include components formed from very thin layers, such as the tunnel oxide layer that exists beneath a gate stack. In order to fabricate the semiconductor devices, subsequent layers of components must be aligned to the thin components. For example, the floating gate and control gate of a gate stack need to be aligned so as to be above the tunnel oxide layer. This can be accomplished by aligning the gate stacks with respect to a select gate oxide formed from the thin layer. In order to ensure that subsequent components are above the appropriate structures, an alignment mark for the thin layer is typically used.
FIG. 1 depicts a conventional method 10 for providing a conventional alignment mark for a thin layer, in particular a tunnel oxide layer. FIG. 1 will be described in conjunction with FIGS. 2A through 2C, which depict a portion of a conventional flash memory device 30 during fabrication. Referring to FIGS. 1 and 2A-2C, a thin oxide layer is provided on a semiconductor substrate, via step 12. FIG. 2A depicts the thin oxide layer 36 on the semiconductor substrate 32. For simplicity, the thin oxide layer 36 is depicted as a deposited oxide. However, the thin oxide layer 36 is typically thermally grown, not deposited. The thin oxide layer 36, which will be used for the select gate oxide, is typically between one hundred and two hundred Angstroms thick, and is often approximately one hundred and forty Angstroms thick. Also depicted in FIG. 2A is a field oxide region 34 that may be used to separate portions of the flash memory device 30.
A mask for the thin oxide layer is then provided, via step 14. Typically, step 14 includes spinning a layer of photoresist onto the flash memory device 30 and exposing the photoresist to print a pattern on the photoresist. FIG. 2B depicts the flash memory device 30 after step 14 has been performed. Thus, a mask 38 has been formed on the thin oxide layer 36. The mask 38 includes portions 40 and 42 that are used to mask the part of the thin oxide layer 36 that will become the select gate oxide layers. The tunnel oxide is self-aligned and will be formed in the region between the portions 40 and 42 of the mask 38, after the portion of the thin oxide layer 36 between the portions 40 and 42 of the mask 38 is removed. The mask 38 also includes a conventional alignment mark portion 44 which is above another part of the thin oxide layer 36 away from the field oxide region 34. The conventional alignment mark portion 44 of the mask 38 is used to provide the conventional alignment mark. The conventional alignment mark will be used to align subsequent masks to ensure that the gate stacks are aligned with respect to corresponding portions of the tunnel oxide layers.
The thin oxide layer 36 is then etched, via step 16. Portions of the thin oxide layer 36 exposed by the mask 38 are thus removed. The mask is then stripped, via step 18. FIG. 2C depicts the flash memory device 30 after removal of the mask 38. The select gate oxide layers 46 and 48 and the conventional alignment mark 50 remain from the thin oxide layer.
The conventional alignment mark 50 is then used to align subsequent structures to the select gate oxide layers 46 and 48, via step 20. Processing of the flash memory device 30 is then continued, via step 22. Thus, a semiconductor device, such as a flash memory device, can be fabricated.
Although the method 10 using the conventional alignment mark 50 functions, one of ordinary skill in the art will realize that alignment using the conventional alignment mark 50 is difficult. Typical alignment tools utilize the interference of light reflected off of the top and bottom interfaces of the conventional alignment mark 50 in order to locate the conventional alignment mark 50. The interference pattern depends upon the path difference between light reflecting off of the top interface of the conventional alignment mark and light reflecting off of the bottom interface of the conventional alignment mark 50. This path difference is converted into a phase difference that is given by 2ntxcfx80/xcex, where n is the index of refraction of the thin oxide layer of which the conventional alignment mark is made, t is the thickness of the conventional alignment mark, xcex is the wavelength of light used and the path differences is 2nt. There is a strong contrast (destructive interference) when the phase difference is close to xcfx80; this maximizes the difference in signal intensity between the mark (high intensity) and the background (low intensity).
Often, light having a wavelength of approximately six hundred and thirty three nanometers (six thousand three hundred and thirty Angstroms) is used. The thickness of the conventional alignment mark is determined by the thickness of the thin layer 36 and is, therefore, on the order of one hundred to two hundred Angstroms. The index of refraction for the thin layer is often not significantly greater than one (on the order of 1.4). Thus, the phase difference due to the conventional alignment mark 50 is very small. As a result, the conventional alignment mark 50 will not result in an interference pattern with a great deal of contrast. Consequently, the conventional alignment mark 50 may be difficult to use. As a result, processing is more difficult and the probability of misalignments is increased.
Accordingly, what is needed is a system and method for providing a more robust, or simpler to find, alignment mark for use with structures formed in thin layers. The present invention addresses such a need.
The present invention provides a method and system for providing an alignment mark for a thin layer in a semiconductor device. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system comprise providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system comprise providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also comprise removing a portion of the alternative part to provide the alignment mark in the at least one alternative part.
According to the system and method disclosed herein, the present invention provides an alignment mark which is simpler to find and which does not complicate processing of the semiconductor device.